1. Field of the Invention
The present invention relates to a demodulator using quasi-synchronous detection to demodulate modulated quadrature input signals. More particularly, the present invention relates to a demodulator having a quasi-synchronous detector to detect a modulated quadrature input signal using an output signal of a fixed frequency from a local oscillator, an equalizer to equalize a quadrature channel signal which is a digital signal converted from the detected quadrature signal output from the quasi-synchronous detector, and a phase rotator to rotate the phase of the quadrature channel signal output from the equalizer.
The demodulator that demodulates modulated quadrature signals has a configuration comprising numerous digital processing sections. Consequently, the configuration for quasi-synchronous detection is generalized. To reduce the equipment costs on the transmitting side, a local oscillator of relatively low-cost configuration is used. However, the oscillating frequency of this oscillator fluctuates. Therefore, the invention relates to a demodulator for use on the receiving side that follows the fluctuating frequency and modulates received signals without complicating the configuration and generating increased costs.
2. Description of the Related Art
FIG. 1 is a schematic block diagram of a prior art demodulator regenerating an analog carrier. In this figure, the demodulator has an input terminal 101; a synchronous detector 102 for quadrature synchronous detection; a local voltage controlled oscillator (LVCO) 103; band-pass filters 104 and 105 for shaping roll-off waveforms; A/D converters 106 and 107; a constant-voltage clock oscillator (CVCO) 108; a transversal equalizer 109; a controller 110; low-pass filters 111 and 112; and output terminals 113 and 114 for channels I and Q that are perpendicular to one another.
To output the detected signals of quadrature channels I and Q, the synchronous detector 102 detects modulated quadrature signals input into the input terminal 101 synchronously using output signals from the local voltage controlled oscillator 103. The detected output signals are input into the A/D converters 106, 107 via the band-pass filters 104, 105. The signals are sampled using clock pulses from the constant-voltage clock oscillator 108, converted into digital signals, and input into the transversal type automatic equalizer 109. The equalization-evaluated I-channel and Q-channel output signals are output to the post-stage devices from the output terminals 113, 114.
Based on the equalization-evaluated output signals (baseband signals), the controller 110 calculates the phase difference between the carrier of a modulated A quadrature signal and the regenerated carrier. The controller 110 then applies a control voltage according to the calculated phase difference to the local voltage controlled oscillator 103 through the low-pass filter 111. The controller 110 synchronizes the regenerated carrier phase of a signal output from the local voltage controlled oscillator 103 with the carrier phase of a modulated quadrature signal input from the input terminal 101. The controller 110 applies a control voltage to the constant-voltage clock oscillator 108 through the low-pass filter 112 to synchronize the phase of the clock signal input into the A/D converters 106, 107 with the symbol phase.
In the demodulator regenerating an analog carrier, the delay time is increased by containing band-pass filters 104, 105, A/D converters 106, 107, an equalizer 109, a controller 110, and a low-pass filter 111 in the generation loop. As a result, it becomes difficult to follow the fluctuating carrier phase of a modulated quadrature signal at high speeds.
FIG. 2 is a schematic block diagram of a prior art demodulator regenerating a digital carrier. In this figure, the demodulator has an input terminal 121; a quasi-synchronous detector 122; a local oscillator 123; band-pass filters 124 and 125; A/D converters 126 and 127; a constant-voltage clock oscillator 128 for clock pulse output; a transversal equalizer 129; a phase rotator 130; a constant-voltage phase control signal oscillator 131; a controller 132; low-pass filters 133 and 134; and output terminals 135 and 136.
The local oscillator 123 has a preset oscillation frequency for oscillating a signal having the same frequency as the carrier frequency of the modulated quadrature signal (intermediate frequency) input from the input terminal 121. Therefore, if the quasi-synchronous detector 122 is set so that it corresponds with the synchronous detector 102 shown in FIG. 1, the phase and frequency of the regenerated carrier is deviated from the phase of the carrier of the modulated quadrature signals. In accordance with this deviation, the phases of I-channel and Q-channel detection output signals are rotated.
The I-channel and Q-channel output signals from the quasi-synchronous detector 122 are input into the A/D converters 126, 127 through the band-pass filters 124 and 125. These signals are sampled using the clock pulses from the constant-voltage clock oscillator 128 to be converted into digital I-channel and Q-channel signals. If the quadrature signals modulated by quadrature amplitude modulation ("QAM") are input into the input terminal 121, the A/D converters 126, 127 sample the I-channel and Q-channel signals by using the clock pulses to convert them into 8-bit digital signals.
If the digital I-channel and Q-channel signals are input into the phase rotator 130, the phase rotator 130 multiplies the input signals by phase control signals from the constant-voltage phase control signal oscillator 131 to rotate their phases. Consequently, the I-channel and Q-channel signals of quasi-synchronous detection are controlled to keep almost the same phases as those of synchronous detection. The I-channel and Q-channel signals output from the phase rotator 130 are equalization-evaluated by the equalizer 129, corresponding to the equalizer 109 of FIG. 1. Based on the equalization-evaluated output signals, control signals for the constant-voltage clock oscillator 128 and constant-voltage phase control signal oscillator 131 are output by the controller 132.
The controller 132 outputs control signals on the basis of the polarity bits of the demodulated quadrature-channel (I-channel and Q-channel) output signals from the output terminals 135, 136 and the error signals. In the aforementioned 8-bit configuration, the highest-order bit of a Q-channel or I-channel signal is polarity bit D, the second bit is an effective data bit, and third bit is error signal bit E. The controller 132 then uses the multiplication output or exclusive OR output of I-channel polarity bit D and Q-channel error signal bit E as a control signal. Likewise, the multiplication output or exclusive OR output of Q-channel polarity bit D and I-channel error signal bit E may also be used as a control signal.
FIG. 3 is a schematic diagram further illustrating the details of the phase rotator 130 and the constant-voltage phase control signal oscillator 131 shown in FIG. 2. In this figure, phase rotator 130 includes multipliers 141 through 144 and adders 145 and 146, and oscillator 131 includes delay elements (T) 151 and 152; an adder 153; and a memory device 154, usually read-only memory (ROM), where sin .theta. and cos .theta. are stored for an accumulated value.
The controller 132 in FIG. 2 inputs a control signal to the phase control signal oscillator 131 through the low-pass filter 134. This signal is input into the adder 153 through the delay element 151. The output from the delay element 151 is added to the previous output through the delay element 152 to determine an address in the memory device 154.
With the accumulated value of the control signals as a memory address, sin .theta. and cos .theta. are read from the memory device 154. The sin .theta. is input into the multipliers 142, 143 and the cos .theta. into the other multipliers 141, 144.
If the input I-channel and Q-channel signals of the phase rotator 130 are I' and Q' and the output I-channel and Q-channel signals from the adders 145, 146 are I" and Q", the following equations apply: EQU I"=I' cos .theta.-Q' sin .theta. (1) EQU Q"=I' sin .theta.+Q' cos .theta. (2)
When the frequency or phase of an output signal from the local oscillator 123 in FIG. 2 does not match that of the carrier of a modulated quadrature input signal, the phases of the I-channel and Q-channel signals from the quasi-synchronous detector 122 may change. Even under these conditions, the phase rotator 130 can rotate the I-channel and Q-channel signal phases to achieve the specified phases. Consequently, the demodulator of FIG. 2 can output quadrature channel signals as if the modulated quadrature input signals have been detected synchronously, using the regenerated carriers in phase synchronism with those of the modulated quadrature input signals.
FIG. 4 is a schematic diagram further illustrating the details of the transversal equalizer 129 shown in FIG. 2. In this figure, elements 129-1 and 129-2 are equalizers for channels I and Q. An equalizer 129-1 includes tapped delay circuits 141 and 144 consisting of flip-flops, multipliers 142 and 145 and adders 143, 146 and 147. (CI -n . . . CI o . . . CI n) and (CIX -n . . . CIX o . . . CIX n) represent the tap factors input from the controller 132 as further depicted in FIG. 5.
A common-mode filter consists of the tapped delay circuit 141, multiplier 142, and adder 143. A quadrature filter consists of the tapped delay circuit 144, multiplier 145, and adder 146. Since the equalizers 129-1 and 129-2 have the same configuration, details of the channel-Q equalizer 129-2 are omitted in FIG. 4. The equalizers for channels Q and I reduce intersymbol interference by the common-mode filter and eliminate components leaking from channel Q into channel I (or in the opposite direction) by the quadrature filter.
FIG. 5 is a schematic diagram further illustrating the details of the controller 132 shown in FIG. 2. In this figure, elements 132-1 and 132-2 are I-channel and Q-channel controllers. The I-channel controller 132-1 consists of flip-flops (FF) 151 and 157 multiplier 152 and 156, integrators (.intg.) 153 and 155, and n-stage shift register ("SR") 154. DI and DQ represent I-channel and Q-channel polarity bits, while EI and EQ represent I-channel and Q-channel error signals. Since the controllers 132-1, 132-2 have the same configuration, the details of channel-Q controller 132-2 are omitted in FIG. 5.
The flip-flops 151, 157 are connected in 2n stages each by cascade connection. Either input terminal of each multiplier 152, 156 is connected to each tap and the shift register 154 to the other input terminal. I-channel polarity bit DI is input into a flip-flop 151 and Q-channel polarity bit DQ into the other flip-flop 157. I-channel error signal EI is input into the shift register 154.
The integrator 153 integrates (averages) multiplied output signals from a multiplier 152 and outputs the tap factors (CI -n . . . CIo . . . CI n) for the common-mode filter. The integrator 155 integrates (averages) multiplied output signals from a multiplier 156 and outputs the tap factors (CIX -n . . . CIX o . . . CIX n) for the quadrature filter.
FIGS. 3 and 5 illustrate the configuration and function of each section in the conventional demodulator shown in FIG. 2 which regenerates a digital carrier. The configurations and functions of such a demodulator are also described in Japanese Patent Publication Nos. 6-85864, 6-90265, and 6-152676. For a system containing this kind of demodulator, a high-precision oscillator is recommended as a carrier oscillator for modulated quadrature signals on the transmission side. However, taking this course of action will incur high costs.
To reduce equipment costs, however, low-cost oscillators can be used, although precision is sacrificed to some extent. That is, these oscillators cause relatively large phase and frequency fluctuation of the carrier of a received modulated quadrature signal. For the transmission of dynamic images, high-speed transmission (several Mega bps or more) is required even when the data is compressed. If the carrier frequency displays relatively large fluctuations in high-speed transmission, the phase rotator 130 should be controlled so that it follows the fluctuations of the carrier phase and frequency.
The loop for controlling the phase rotator 130 contains an equalizer 129. Since this equalizer 129 has tapped delay circuits containing multistage flip-flops, the delay is relatively significant. This makes it difficult to control the phase rotator 130 at high speeds.
FIG. 6 is a schematic of a prior art demodulator of the type proposed to reduce delay in the loop for controlling the phase rotator. In this figure, the demodulator has an input terminal 161; a quasi-synchronous detector 162; a local oscillator 163; band-pass filters 164 and 165; A/D converters 166 and 167; a constant-voltage clock oscillator 168 for clock pulse output; a transversal equalizer 169; a phase rotator 170; a constant-voltage phase control signal oscillator 171; a controller 172; low-pass filters 173 and 174; and output terminals 175 and 176.
Compared to the demodulator shown in FIG. 2, the demodulator shown in FIG. 6 has equalizer 169 at the prior stage of phase rotator 170. Therefore, the loop for controlling the phase rotator does not contain the equalizer. By reducing the loop delay in this manner, the phase rotator can be controlled so that it follows the carrier phase and frequency fluctuations of modulated quadrature input signals at high speed.
FIG. 7 is a schematic view of another prior art demodulator. In this figure, the demodulator has an input terminal 181; a quasi-synchronous detector 182; a local oscillator 183; band-pass filters 184 and 185; AID converters 186 and 187; a constant-voltage controlled clock oscillator 188; a forward-tap equalizer 189A; a backward-tap equalizer 189B; phase rotator 190; a constant-voltage phase control signal oscillator 191; a controller 192; low-pass filters 193 and 194; and output terminals 195 and 196.
The equalizer 169 in FIG. 6 for use in the demodulator of FIG. 7 is separated into the forward-tap equalizer 189A and backward-tap equalizer 189B and the phase rotator 190 is connected between them. For example, the forward-tap equalizer 189A is a forward type transversal equalizer and the backward-tap equalizer is a backward type equalizer 189B performing evaluation feedback.
The I-channel and Q-channel signals are equalized by the forward-tap equalizer 189A and controlled by the phase rotator 190 so that the I-channel and Q-channel signals are regulated to the normal demodulation phases. These signals are then equalization-evaluated by the backward-tap equalizer 189B. The backward-tap equalizer 189B causes a delay of about only one symbol. Even when the loop for controlling the phase rotator 190 contains the backward-tap equalizer 189B, high-speed follow-up control can be provided. This demodulator is also described in Japanese Patent Publication No. 7-66843.
The prior art demodulators shown in FIGS. 6 and 7 enable high-speed phase control by reducing the delays in the loops for controlling the respective phase rotators 170, 190. Unlike the prior art demodulators shown in FIGS. 1 and 2, however, this demodulator has the equalizer 169 or forward-tap equalizer 189A outside the phase control loop. Therefore, the phases of the input I-channel and Q-channel signals are rotating. In other words, the equalizer 169 or forward-tap equalizer 189A operate in the rotating coordinate system. Meanwhile, the controllers 172, 192 are inside the phase control loop and the phases of the input I-channel and Q-channel signals are not rotating. In other words, the controllers 172, 192 operate in the nonrotating coordinate system. Since control signals produced by a static coordinate system are not correct for the equalizers operating on the rotating coordinate system, control is unstable.
Phase-rotated I-channel and Q-channel signals are input into the controllers 172, 192 and tap factors to add to the equalizer 169 or forward-tap equalizer 189A are generated. Therefore, the tap factors are changed at every phase rotation control by the phase rotators 170, 190. Although the phase rotation can be controlled at high speeds so that it follows the carrier phase and frequency of the modulated quadrature input signal, the equalization processing at the prior stages of the phase rotators 170, 190 become unstable.